                              ===========================                             
                              R E L E A S E    N O T E S
                              ===========================

                         QLogic 5709/5716 Gigabit Ethernet Controller Bootcode

                      Copyright (c) 2015 QLogic Corporation
                                 All rights reserved.

Known issues
============

None.


History
=======

Version 7.4.0 (September 06, 2012)
=================================

    Fixes:
    ------
    1.  Problem: False alarms on PCIE flow control error are detected by
                 some systems, causing the systems to stop booting 
                 (CQ#64263).
                 
        Cause:   False alarms may occur during the PCIE link 
                 establishment. Some BIOS do not reset these error
                 indications.

        Fix:     Since the PCIE flow control check is optional, it is 
                 now removed.

        Impact:  None.


Version 6.2.0 (November 17, 2010)
=================================

    Fixes:
    ------
    1.  Problem: In some mezz designs for one OEM, the license may 
                 become invalid when an OEM specific feature thru EFI 
                 driver is applied (CQ#50415).
                 
        Cause:   When such a feature is applied, the MAC address is
                 changed, causing license to become invalid.

        Fix:     Detect for certain mezz designs. If so, apply the
                 license validation algorithm again with MAC address
                 stored elsewhere when the first attempt fails.

        Impact:  The second check is isolated to certain mezz designs.


Version 6.0.0 (August 16, 2010)
===============================

    Enhancements:
    -------------
    1.  Request: Provide OEM specific firmware workaround to prevent 
                 Cu PHY link flap during case specific system-POST phase
                 (CQ#49362).

        Changes: This change is gated by an NVRAM configuration only
                 applicable for specific OEM platform.

        Impact:  There is no impact for existing shipping platforms. This 
                 feature has to be specifically enabled in the NVRAM
                 configuration via xdiag/lxdiag.


Version 5.2.3 (April 29, 2010)
==============================

    Fixes:
    ------
    1.  Problem: In some LOM designs, PCIE come up as Gen1 after warm
                 reboot (CQ#47387).
                 
        Cause:   This issue is a continuation scenario of CQ#41779, in
                 which the system BIOS issues a back-to-back #PERST.
                 These back-to-back resets cause the bootcode to reset
                 the entire chip (see bootcode v5.0.7 for more details),
                 wiping out our Gen2 capability advertisement and 
                 triggering the bootcode to reload. The reload time 
                 takes slightly longer that the bootcode cannot re-
                 advertise Gen2 capability before the PCIE training.
                 Thus, the link comes up in Gen1 mode. Although we have
                 a forced retrain mechanism (see fix #1 in v5.0.0, 
                 CQ#39159), it was only applicable to NIC designs.

        Fix:     Enable the same fix introduced in v5.0.0 (see 
                 CQ#39159), which was limited to NICs, but is now made 
                 available to LOM designs. In essence, the bootcode will 
                 initiate a PCIE retraining in Gen2 mode after it sees 
                 the Gen2 capability advertisement from the link 
                 partner.

        Impact:  The logic only kicks in when the link comes up as Gen1
                 while both RC and endpoint are Gen2 capable. Thus,
                 systems that consistently come up as Gen2 will not
                 have this logic executed and therefore will not have
                 any exposure to this change.


    Enhancements:
    -------------
    1.  Request: Prevent PCIE L1 entry as a workaround for some 
                 incompatible chipset (CQ#47220).

        Changes: Defined an NVRAM configuration bit. When the bit is
                 set, the bootcode will configure the hardware from
                 going to L1 state.

        Impact:  Minimal since it's gated by an NVRAM configuration bit. 
                 Other existing designs are not affected by this.


Version 5.2.2 (November 17, 2009)
=================================

    Fixes:
    ------
    1.  Problem: Windows may hang at bootup time if VBD has MSI-X
                 enabled (CQ#43420, CQ#43504).
                 
        Cause:   The MSI-X table setup is done once during system
                 POST. If the device gets a reset (e.g. due to a pre-
                 boot driver loads up) prior to Windows loading up, the 
                 table setup is wiped out, preventing Windows from 
                 programming the table properly. As a result, the VBD 
                 may not load up correctly and cause unexpected behavior 
                 (e.g. BSOD).

        Fix:     Initialize the MSI-X table on every port reset.
                 
        Impact:  Introduced in T5.2. The problem is not exposed on Linux 
                 because bnx2 configures the table setup on its own.


    Enhancements:
    -------------
    1.  Request: Validate UVLK for some specific OEMs (CQ#44540,
                 CQ#44545).

        Impact:  Only for specific OEMs.


Version 5.2.1 (October 16, 2009)
================================

    Fixes:
    ------
    1.  Problem: When a system is under an extreme stress, host may 
                 suddenly lose incoming traffic (CQ#42907).
                 
        Cause:   Under this condition, bootcode may be misled to think
                 that the OS is gone because the host driver has no
                 resource to send alive pulses within a 6-second timeout
                 period. Thus, bootcode configures the chip to re-route 
                 packets to management firmware directly.

        Fix:     Extend the timeout period to five minutes to minimize
                 any false alarms due to heavy system stress. Also, 
                 upon timeout, the bootcode will leave the traffic 
                 routing setup alone since the Rx pipe inside the chip
                 is not stalled at the time; only the OS present 
                 indication in shared memory will be updated. If the 
                 driver starts sending alive pulses again, the shared
                 memory will be updated to reflect the OS presence.
                 
        Impact:  The symptom is seen only when management firmware is
                 enabled.


    Enhancements:
    -------------
    1.  Request: Support an additional license check for one OEM NIC 
                 design (CQ#43655).

        Changes: Add another license check in case the default one 
                 fails. This is applied only for one particular design,
                 eliminating any side effects on others.

        Impact:  None.


    2.  Request: Add configurability on the driver pulse timeout period.

        Changes: Defined a per-port storage space in shared memory to 
                 allow driver to change the driver pulse timeout period
                 at runtime.

        Impact:  Minor code size increase.


    3.  Request: Optimize code spaces.

        Changes: De-featured the unused license expiration check. 
                 Simplify the debug check on detecting old mgmt 
                 firmware.

        Impact:  Should have none since the feature is unused and the 
                 debug check does not affect the overall functionality.


    4.  Request: Add configurability on the driver pulse timeout period.

        Changes: Defined a per-port storage space in shared memory to 
                 allow driver to change the driver pulse timeout period
                 at runtime.

        Impact:  Minor code size increase.


    5.  Request: Take over traffic for mgmt when Rx firmware pipeline 
                 is stalled.

        Changes: Defined an interface to allow RXP firmware to send 
                 keep alive messages. If no new messages after a timeout
                 period, bootcode configures the hardware to re-route
                 traffic to mgmt processor directly. The re-routing is 
                 reversible, should RXP firmware continues to send 
                 messages again. The timeout period is configurable at
                 runtime.

        Impact:  This feature kicks in only when RXP indicates its 
                 ability to send alive messages. 


Version 5.2.0 (August 12, 2009)
===============================

    Fixes:
    ------
    1.  Problem: The expansion ROM hardware setting may be wrong in 
                 certain case even if force expansion rom advertisement
                 is set in NVRAM.
                 
        Cause:   If BIOS issues a port reset to the device after PCIE
                 reset, it clears all expansion ROM hardware setting 
                 while its advertisement remains. When BIOS requests 
                 ROM data, nothing is returned.

        Fix:     Upon detecting a port reset, boot code restores the 
                 expansion ROM settings if force expansion rom 
                 advertisement is set in NVRAM.
                 
        Impact:  This problem was introduced in version 5.0.6 to address
                 CQ#41875, and the exposure is only limited to the issue
                 found in CQ#36352.


    Enhancements:
    -------------
    1.  Request: Need to configure the PCIE Gen2 de-emphasis values for
                 some LOM designs (CQ#42547).

        Changes: Introduced NVRAM bits and boot code programs the Gen2
                 serdes according to the bit value.

        Impact:  None.


Version 5.0.7 (August 04, 2009)
==============================

    Fixes:
    ------
    1.  Problem: If two PCIE back-to-back resets occur somewhere between
                 60 and 80 msec apart, the hardware may hang PCIE 
                 transactions (CQ#41779).

        Cause:   The second PCIE reset creates an unprepared powerdown
                 scenario, and it is left unhandled. This caused some
                 hardware in bad state (e.g. PCIE FC credit).

        Fix:     Upon detecting such a condition, boot code issues a
                 hard reset to bring the hardware back to a good state.


Version 5.0.6 (June 9, 2009)
==============================

    Enhancements:
    -------------
    1.  Request: Program expansion ROM base address register if force
                 expansion rom advertisement is set in NVRAM (CQ#41875).

        Changes: This version will program expansion ROM base address
                 register if force expansion rom advertisement is set 
                 in NVRAM.

        Impact:  None.


Version 5.0.5 (May 22, 2009)
==============================

    Fixes:
    ------
    1.  Problem: Under Linux, connection to management firmware dropped
                 after bringing up the interface and configuring an IP
                 address (CQ#41376). 
 
        Cause:   There is a chip core reset flag set for management 
                 firmware to reprogram the BMC MAC address. The flag
                 has been cleared prematurely that by the time when 
                 bootcode dispatches management firmware, it is not 
                 aware of chip core reset and the BMC MAC address is
                 lost.
 
        Fix:     Do not clear the chip core reset flag until after
                 management firmware has been dispatched.
 
        Impact:  This checking was introduced in version 5.0.2.


Version 5.0.4 (May 21, 2009)
==============================

    Fixes:
    ------
    1.  Problem: Under Linux, connection to management firmware dropped
                 after bringing up the interface and configuring an IP
                 address (CQ#41376). 
 
        Cause:   The handshake between bootcode and driver in this case
                 leads to bootcode skip touching any port registers.
                 As a result, bootcode skips setting EMAC enable flag 
                 even if EMAC has been enabled. Management firmware
                 does not get dispatched because EMAC enable flag has
                 not been set.
 
        Fix:     Do not skip checking if EMAC has been enabled and set
                 EMAC enable flag appropriately.
 
        Impact:  This checking was introduced in version 5.0.2.
                 

Version 5.0.3 (May 20, 2009)
==============================

    Fixes:
    ------
    1.  Problem: System crashes when re-enabling Windows driver (VBD) 
                 on a quad-port NIC (CQ#40098, 5709C). 
 
        Cause:   In conjunction with specific PCI-E bridge vendor, 
                 during the L0 to L1 transition when in D3Hot, the 5709 
                 exposes a bridge anomaly, or limitation that causes a 
                 fatal error to occur on the PCI-E link, that in return
                 is reported by the system as an NMI.  
 
        Fix:     In order to work around this interoperability issue in
                 conjunction with specific PCI-E bridge vendors, this 
                 new boot code enables a feature inside the 5709-C1 
                 silicon that can successfully avoid the NMI condition 
                 to occur.
 
        Impact:  The quad-port NIC design is introduced in 5.0. There
                 should be no exposure to prior releases.
                 
    2.  Problem: If driver pulse timer expires right after bootcode
                 sends link change event to driver, the two back-to-
                 back events may confuse the driver.
                 
        Cause:   Driver pulse timer runs as long as driver is loaded.
                 If this timer expires, it will send an event to driver
                 checking if driver is still alive. If this hapens
                 right after bootcode sends link change event to driver,
                 the driver pulse event may overwrite the link change
                 event, depending on how soon the driver can handle each 
                 event.

        Changes: This code resets the driver pulse timer after sending a
                 link change event to driver to avoid a small chance of
                 sending a driver pulse event if timer expires right 
                 after link change event.
                 
        Impact:  Previous versions of bootcode may experience this 
                 problem. The back to back events sent to driver may 
                 confuse the driver, depending on how soon each 
                 event is served by driver.


Version 5.0.2 (April 24, 2009)
==============================

    Fixes:
    ------
    1.  Problem: Some compilation directives may cause bootcode to 
                 malfunction.
    
        Cause:   There were compilation directives for Serdes or Copper
                 PHY left in dual media bootcode source. Some media 
                 dependent logic were executed without proper checking 
                 for media type.
                 
        Fix:     Added media checking for those logic.
        
        Impact:  This only applies in T5.0.
        
    2.  Problem: Bootcode wrongly assumes that driver is dead and takes 
                 control of device. This may cause BSOD or driver 
                 bug_check (CQ#40266).
                 
        Cause:   Certain version of Windows VBD driver does not write 
                 driver pulse to proper location.
                 
        Fix:     If driver is loaded and driver pulse is absent, check
                 for chip activity register as well to determine driver
                 is still alive before bootcode takes control of device.
                 
        Impact:  This bootcode will be backward compatible with T4.6
                 drivers. The previous versions of bootcode do not
                 expose this problem since they do not check driver
                 pulse properly and see that driver is always alive.

    3.  Problem: Management firmware may be dispatched too soon before
                 chip is fully initialized during driver load.
    
        Cause:   The management firmware dispatch logic does not check 
                 if chip has been fully initialized by driver.
                 
        Fix:     Check for chip initialized fully before dispatching 
                 management firmware.
                 
        Impact:  This avoids the unlikely occurrence that management 
                 firmware starts traffic before the chip is fully 
                 initialized. No report has been received regarding 
                 this problem on previous versions of bootcode.
                 
    4.  Problem: Missing driver pulse counter mistakenly gets 
                 incremented. This causes unnecessary interrupt 
                 generated.
    
        Cause:   Timer value did not get restore after generating 
                 interrupt. It is set to 0.
                 
        Fix:     Restore original timer counter after generating 
                 interrupt.
        
        Impact:  Previous versions of bootcode may experience this
                 problem after link change event happens. But it should
                 not be a problem since they see that driver is always
                 alive.
       
    5.  Problem: Link status polarity reversed on certain system 
                 (CQ#40171).
    
        Cause:   Bootcode sent 2 event interrupts to driver back-to- 
                 back. The second one overwrote the event code of the 
                 first one.
                 
        Fix:     After problem 4 has been fixed, this gets fixed as 
                 well.
        
        Impact:  Previous versions of bootcode may experience this 
                 problem. The back to back events sent to driver may 
                 confuse the driver, depending on how soon each 
                 interrupt is served by driver.
                 

Version 5.0.1 (April 02, 2009)
==============================

    Fixes:
    ------
    1.  Problem: Certain OEM NIC design stalled on one of the slots
                 of one OEM system caused system to hang during boot
                 (CQ#39564).
                 
        Cause:   That OEM NIC design needed special handling of hard
                 resetting the chip to put it in OOB state. That
                 logic might cause race condition.

        Fix:     Added a small delay before hard resetting the chip
                 to avoid race condition.
                 
        Impact:  This logic is applied to an OEM NIC design only.                 


    Enhancements:
    -------------
    1.  Request: Dual media support.

        Changes: This version will support a mixture of either copper or 
                 serdes media per port.

        Impact:  This allows each port to have copper or serdes media
                 instead of both ports to have copper or serdes.
                 
    2.  Request: Due to expanded bootcode size and limited MCP scratch pad
                 space, bootcode 5.0.1 or above will only loads NCSI version
                 1.0.7 or above or IPMI version 1.0.0 or above. The new 
                 management firmware has reduced code size to coexist with
                 bigger bootcode size.
                 
        Changes: With bootcode 5.0.1 or above, NCSI version below 1.0.7 and
                 IPMI version below 1.0.0 will not be run even though they
                 are installed in NVRAM and enabled.
                 
        Impact:  Older version of management firmware will not run.                 


Version 5.0.0 (March 16, 2009)
==============================

    Fixes:
    ------
    1.  Problem: PCIE Gen2 link may not train up on some systems
                 on rebooting from Windows (CQ#39159, found on
                 a quad port NIC design).

        Cause:   On Windows shutdown, boot code puts the chip in
                 MIN_POWER state. This causes a power-on reset, which
                 wipes out PCIE Gen2 advertisement. On the next boot,
                 the boot code fails to advertise Gen2 capability soon
                 enough. As a result, the chip intermittently may come
                 up as Gen1.

        Fix:     Upon detecting the condition of Gen1 while detecting
                 Gen2 capability on the partner, the boot code will
                 advertise Gen2 and issue a speed change request to 
                 upstream to establish Gen2.


    2.  Problem: Back-to-back may not link up when set to forced link
                 (CQ#39501, 5709/16C).

        Cause:   The force auto MDIX mode is not turned on.

        Fix:     Turn on this mode whenever the link is configured.


    3.  Problem: BMC traffic may stop when OS crashes, and mgmt FW
                 may mis-report the OS status (present vs. absent).

        Cause:   The issue comes in two folds. First, the interrupt
                 generation due to remote PHY link change fails to
                 restore the interrupt setting, which is needed to 
                 detect any timeout from driver pulses. As a result, 
                 timeout never occurs, and boot code cannot detect OS 
                 absent event. Second, if the OS crash is due to Rx 
                 pipeline stall, the stall itself can also stall all 
                 BMC traffic.
        
        Fix:     Use a slightly different way to determine timeout.
                 Also, re-route traffic directly to mgmt FW instead of
                 letting packets to traverse through the normal path.

    4.  Problem: 5709 NIC WOL failed intermittently on one system
                 (CQ#39322).

        Cause:   On Windows shutdown with certain system, boot code
                 puts the chip in MIN_POWER state. This will stop
                 the system from waking up.

        Fix:     Upon shutdown, boot code sets chip in MIN_POWER
                 state only when it is in OOB condition.


    Enhancements:
    -------------
    1.  Request: Optimize code spaces.

        Changes: Changed all debug traces to functions rather than
                 macros.

        Impact:  Saved code spaces while preserving all functionalities.


    2.  Request: Accommodate the new NCSI firmware single image format.

        Changes: The new NCSI firmware will be a single image, rather
                 than two separate ones. Boot code checks for firmware
                 version to decide whether to load the second image or
                 not.

        Impact:  Added a generic firmware version lookup.


Version 4.6.5 (November 21, 2008)
=================================
 
    Fixes:
    ------
    1.  Problem: PCIE Gen2 link may not train up on some systems.

        Cause:   (1) The PCIE Gen2 capability is advertised late. The
                 internal memory BIST could be causing the delay. (2)
                 PCIE reset may disrupt the boot code operation, invoked
                 by power on reset. This could prevent Gen2 
                 advertisement.

        Fix:     (1) Swap the BIST operation and Gen2 advertisement. (2)
                 Advertise Gen2 capability and initialize PCIE block
                 even on PCIE reset.


    2.  Problem: Some chip blocks needed by management firmware are 
                 enabled when it is disabled temporarily in manfacturing
                 diagnostic environment.

        Cause:   The blocks are enabled by the NVRAM configuration. In
                 the case where management firmware is temporarily
                 disabled, the NVRAM configuration is not changed.

        Fix:     Check whether management firmware is actually loaded
                 rather than on the NVRAM configuration before deciding
                 on enabling those chip blocks.


    Enhancements:
    -------------
    1.  Request: Include 5716S support.

        Changes: Include chip bond ID check for 5716S.

        Impact:  None.


    2.  Request: Improve power savings.

        Changes: Enable the powerdown of unused PCIE lanes.

        Impact:  None.


    3.  Request: Stop supporting A0.

        Changes: Removed any A0 specific workarounds.

        Impact:  Some code size savings.


    4.  Request: Add memory parity checking.

        Changes: With BIST matured, enable the memory parity feature
                 in the hardware.

        Impact:  Upgrading boot code from version before 4.4.2 will
                 require power cycle of the system. Otherwise, false
                 parity errors may occur.


Version 4.6.4 (October 17, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: MSI is only using one message on Windows.

        Cause:   Boot code was only advertising eight messages while we 
                 need nine. As a result, the OS defaults back to one.

        Fix:     Advertise the next higher number of supported MSI 
                 messages, which is 16.


    2.  Problem: 5709S remote PHY may experience unexpected link bounce
                 (CQ#37469, 5709S).

        Cause:   In remote PHY application, the link may be established
                 using the incorrect link preference. Previously, boot
                 code was relying on the periodic fallback mechanism to
                 check and possibly restart link auto-negotiation if
                 necessary.

        Fix:     Force an immediate fallback check restart link auto
                 negotiation to restore the link.


    3.  Problem: Link may fail to come up with some remote PHY designs
                 running RHEL (CQ#35993, 5709S).

        Cause:   The problem was originally found in 5708S, but 5709S
                 may be susceptible to this.

        Fix:     Change the remote copper PHY default link preference to
                 match that of bnx2, avoiding the copper link down
                 during RHEL boot up.


    4.  Problem: WOL on 5709S NIC works while it shouldn't (CQ#37836,
                 5709S NIC).

        Cause:   Boards may be mis-configured to allow this.

        Fix:     On 5709S NIC, the WOL enable bit is filtered out when
                 transferring NVRAM content to shared memory. This 
                 effectively prevents WOL from kicking in.

        Impact:  5709S NIC design only.


    5.  Problem: Windows occasionally creates new network interface 
                 instances after reboot (CQ#37358).

        Cause:   From cold boot, the device serial number in shared
                 memory is incorrect. The shared memory is eventually
                 updated correctly. The system at this points has 
                 already enumerated the device based on the incorrect 
                 serial number. This in itself is not a problem until 
                 the next reboot. Upon reboot, the correct serial number 
                 is now present, and that causes Windows to re-enumerate 
                 it as a new device.

        Fix:     Fetch the MAC address from the NVRAM before 
                 initializing the device serial number, ensuring a 
                 consistent and correct value on every cold boot.


    6.  Problem: The power consumption and dissipation numbers at the 
                 PCIE configuration space may be mis-reported on the 
                 second port.

        Cause:   Similar to issue #5 above, on cold boot, the second
                 port may report power numbers of zero. This is simply
                 a display issue, and there is no functional impact.

        Fix:     Fetch the power numbers stored in NVRAM to the shared 
                 memory for the second port at an earlier point to 
                 display the correct numbers.


Version 4.6.3 (September 22, 2008)
==================================
 
    Fixes:
    ------
    1.  Problem: IPMI traffic stops on system shutdown (CQ#36812).

        Cause:   One port has its driver gracefully unloaded during RHEL
                 boot up time since there is no link partner. This is 
                 considered a prepared powerdown, but the remote console 
                 forces a ungraceful system shutdown. This system power 
                 down (prepared on one port but unprepared on the other) 
                 disables the driver present checking mechanism. As a 
                 result, auto packet forwarding is not enabled, and IPMI 
                 traffic stops.

        Fix:     Force to mark driver absent as soon as the system is
                 powered down (main power gone) and enable packet
                 forwarding if mgmt FW is enabled.


    2.  Problem: Driver enumerates iSCSI on 5716 device.

        Cause:   The enumeration value in the NVRAM was inadvertently
                 set to enumerate iSCSI driver.

        Fix:     Force to enumerate NDIS only and zero out all resource
                 configuration values in the shared memory for 5716.


    3.  Problem: Management firmware reports an invalid link status
                 information to BMC (CQ#37144).

        Cause:   The link status is initialized to 0xFFFFFFFF whenever 
                 a port reset occurs. Mgmt FW may be sending this value
                 to BMC.

        Fix:     Perform link status update before dispatching mgmt FW.


    Enhancements:
    -------------
    1.  Request: As requested by Windows and Linux driver teams, 
                 increase the MSI-X table size from seven to eight.

        Changes: Change the MSI-X table size in the MSI-X initialization
                 routine.

        Impact:  None.


    2.  Request: Strengthen the license validation scheme.

        Changes: Validate the internal shared secret against the SVID
                 and fall back to manuf key if the upgrade key is
                 expired.

        Impact:  Minimal, the shared secret and SVID should already be
                 properly programmed. The license expiration scheme has
                 not been used yet.


    3.  Request: Need license from hardware token to take effect 
                 immediately before driver is loaded (CQ#36910).
    
        Changes: Re-validate license after handshake with BIOS .

        Impact:  Minimal, invoke license validation routine after the
                 successful handshake with BIOS.


Version 4.6.2 (August 11, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Management firmware could mistreat ingress packets
                 when driver is unload (CQ#36679, 5709 C/S).

        Cause:   The boot code fails to update KEEP_VLAN state during 
                 the driver unloading sequence.

        Fix:     Update the KEEP_VLAN state regardless of whether driver
                 is present or absent.


    2.  Problem: Port swapping does not take effect after unprepared
                 powerdown (e.g. DOS shutdown) on LOMs. As a result, WOL
                 works on the wrong port.

        Cause:   The port swapping logic misses to check for hard reset
                 condition to apply the swapping.

        Fix:     Include hard reset check in the port swapping logic. 


    Enhancements:
    -------------
    1.  Request: Reduce unnecessary power consumption on the SerDes. The
                 embedded copper PHY is not completely powered down when
                 the chip is in MIN_POWER mode (CQ#35823, 5709S C0).

        Changes: Added some initialization code from LSI team to allow
                 copper PHY completely powered down.

        Impact:  Added some delay to the overall initialization.


Version 4.6.1 (August 01, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Windows driver asserts when running some traffic stress
                 tests on one OEM design (CQ#35968, 5709 C/S).

        Cause:   Some chipset has an compatibility issue that requires
                 our chip to disable PCIE relax ordering bit.

        Fix:     Added an NVRAM configuration setting support for users 
                 to tweak the relax ordering bit setting to achieve the
                 maximum interoperability with all chipsets.


    2.  Problem: Boot code may ignore the flow control setting when
                 other software entities request a link change
                 (5709 C/S).

        Cause:   The link matching logic is faulty to ignore the flow
                 control. It simply tried to match the speed preference
                 against the current link speed.

        Fix:     Since the original intent for the link matching logic
                 was to preserve link for MBA, but MBA already has the 
                 logic in place, this link matching logic is of no use.
                 Thus, it is eliminated.


    3.  Problem: Need to improve CTX CAM match margin for stability 
                 across PVT (5709 C/S).

        Cause:   CTX CAM BIST is failing on some chips when running at 
                 low voltages. This is a similar change to that in 
                 v4.4.13.

        Fix:     Tweak the CTX CAM match margin on every port reset.
                 Moreover, the tweak is also applied prior to running
                 BIST invoked by the boot code.


    4.  Problem: An OEM system crashed when trying to load PXE 
                 (CQ#36352, 5709 C/S).

        Cause:   BIOS issues a port reset, clearing out all expansion
                 ROM hardware setting while its advertisement remains.
                 When BIOS requests ROM data, nothing is returned.

        Fix:     Upon detecting a port reset, boot code restores the 
                 expansion ROM settings.


    5.  Problem: Some 5716 devices may have iSCSI drivers enumerated
                 (5709 C/S).

        Cause:   The enum_val in the shared memory and NVRAM may have 
                 iSCSI driver enumeration bit set. This bit should be
                 ignored. 

        Fix:     Ignore the NVRAM setting and only enable NDIS in the
                 shared memory.


    6.  Problem: OOB WOL may work only at 10BaseT, even though all 
                 speed capabilities are advertised (5709C).

        Cause:   The set_link() routine is ignoring the speed setting
                 because the "copper" bit is not set.

        Fix:     Set the "copper" bit to let set_link() routine process
                 the link request properly.


    7.  Problem: Chip power consumption is not at its minimum when no
                 WOL nor mgmt FW is enabled on LOMs (5709 C/S).

        Cause:   Boot code did not put the chip in MIN_POWER mode.

        Fix:     The chip is now put to MIN_POWER mode in this case.


    Enhancements:
    -------------
    1.  Request: Advertise bi-directional flow control in the PHY and
                 SerDes by default. Currently, it is doing so only on
                 one direction.

        Changes: Updated the default advertisement.

        Impact:  None.


    2.  Request: 5716 does not support. Thus, the handshake with BIOS
                 for this device is disabled.

        Changes: Identify 5716 and ignore BIOS handshake messages.

        Impact:  None.


Version 4.6.0 (June 13, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Chip internal FIFO parameters require tuning when
                 running in PCIE Gen2 x4 mode (CQ#35868).

        Cause:   An internal data FIFO in the chip could overflow if not
                 tuned.

        Fix:     Limit the TDMA read request to a smaller amount 
                 (256 bytes).


Version 4.4.13 (June 12, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Need to improve CAM match margin for stability across 
                 PVT (5709 C/S).

        Cause:   CAM BIST is failing on some chips when running at low
                 voltages.

        Fix:     Tweak the CAM match margin on every port reset.


Version 4.4.12 (May 29, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: WOL does not work on some blade server designs (5709S).

        Cause:   The checking for inconsistent SerDes link information
                 missed a good case (see CQ#35216 in v4.4.9) when inter-
                 preting SerDes register values. Thus, the boot code
                 mistreated this case and considered the link being 
                 down. Thus, EMAC mode was mis-programmed, and no magic
                 packets can be detected.

        Fix:     Improve the link information checking to handle this 
                 good case properly, allowing the link up to allow WOL 
                 to function.


Version 4.4.11 (May 27, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: DOS shutdown WOL does not work on NICs running on 
                 certain systems (CQ#35501).

        Cause:   The condition check (comparison) in the code was 
                 actually an assignment, causing the chip to report
                 incorrect reset type (Vaux power only rather than full
                 power). This led to the inability to bring the chip
                 back to OOB state when doing to DOS shutdown. This 
                 problem could be exposed in Windows S5 shutdown as 
                 well.

        Fix:     Fixed the condition check to eliminate the inadvertent
                 assignment.


    2.  Problem: LED showing link on shutdown even though WOL is 
                 disabled on an OEM NIC (CQ#35349, 5709C).

        Cause:   While our reference NIC has an external circuit to 
                 control the power to the chip to create a power gap, 
                 this OEM NIC does not appear to have this working. As
                 a result, the boot code continues to operate even when
                 main power is gone from system shutdown. The expected
                 behavior is that upon main power loss, the external 
                 circuit creates a power gap, making the chip loses 
                 power for a short moment. Then, power is restored to
                 create the OOB scenario. If WOL is disabled, the boot
                 code will eventually shut down the PHY and drop the
                 link.

        Fix:     Added a workaround to poll for main power loss and 
                 issue a hard reset to the chip when the condition 
                 occurs. This will create a similar OOB scenario.


Version 4.4.10 (May 23, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Erroneous "PCI-E flow control protocol error" status 
                 reporting leads to false SERR indication (CQ#35407, 
                 5709C A1).

        Cause:   For 5709-A1 devices, a (PCI-E) flow control 
                 synchronization issue exists that erroneously causes 
                 the "uncorrectable error status" register bit[13] to be 
                 set, what in return can lead to an #SERR indication in 
                 the PCI configuration space of the LAN controller.

        Fix:     Skip the OPTIONAL PCI-E flow control protocol error 
                 checking in A1 only.


Version 4.4.9 (May 15, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Link stays up after Windows driver is unloaded on NICs
                 (CQ#35363).

        Cause:   The WOL is enabled in the NVRAM. Boot code mistreated
                 the internal power management state and allowed the 
                 lower power link to come up.

        Fix:     Corrected the internal power management state 
                 treatment.


    2.  Problem: Remote PHY link does not come up when connected to a 
                 forced link partner in Vaux state (5709S).

        Cause:   The link fallback mechanism does not kick in because 
                 the timer is not active in Vaux state. Thus, the timer
                 never expires to trigger the fallback.

        Fix:     Switched the timer from GRC to the processor's internal
                 counter. The timer counts are also adjusted 
                 accordingly.


    3.  Problem: EMAC mode is not set correctly in OS absent case. This
                 could cause management packet loss when set to 2.5G or 
                 half duplex.

        Cause:   The EMAC mode register was not updated properly in 
                 those cases.

        Fix:     Corrected the EMAC mode register update to handle 2.5G
                 and half duplex link.


    4.  Problem: DOS drivers display incorrect remote PHY link speed 
                 when the link is forced (CQ#35321, 5709S). The problem
                 could be exposed in other drivers that do not wait for 
                 link change interrupts.

        Cause:   The driver was reading stale information immediately 
                 after sending link change request.

        Fix:     Force a link down status as soon as the request is
                 received.


    5.  Problem: Windows goes BSOD when booting via iSCSI boot on a 
                 mezz card design when linked at a forced speed via 
                 remote PHY (CQ#35216).

        Cause:   The boot code was reporting stale information from the
                 SerDes. That information gives an inconsistent link
                 info (i.e. local SerDes link up at 100Mbps). This 
                 misled Windows driver to apply incorrect settings,
                 resulting a failure to establish any link.

        Fix:     Force a link down status upon detecting the 
                 inconsistent link information to allow the correct
                 update at a later time. 


Version 4.4.8 (May 08, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Mgmt FW traffic stops after PXE (or iSCSI boot) unloads
                 while link is up (CQ#35103).

        Cause:   The unloading of PXE resets the EMAC mode to hardware
                 default. Since the link remains, the boot code does not
                 have a chance to update the EMAC mode to match the 
                 current link speed. As a result, the EMAC block cannot
                 receive any traffic.

        Fix:     On unloading of driver, boot code will assign an init
                 value to the link status, forcing it to query the PHY
                 (or SerDes) to update the link and configure the EMAC.


    2.  Problem: Windows freezes when disabling or uninstalling drivers
                 (CQ#35028).

        Cause:   Per PCI specification, when the LOM is put into D3-Hot 
                 (D3H), it will initiate the PCI-E link to transtion 
                 from L0 to L1. It is still possible for the system to 
                 'talk' to the LOM while in D3H, using configuration 
                 read and write cycles. So when the upstream chipset is 
                 sending those commands, the link temporarily returns to 
                 L0 before the downstream LOM initiates the link to 
                 return back into L1. The time prior to driving the 
                 PCI-E link back into L1 while in D3H is 8 usec (HW 
                 default). We have observed that this time is rather 
                 aggressive and may cause certain chipsets to lock up 
                 during the L0->L1 transition what may freeze the 
                 system, or can even cause a BSOD, depending on the 
                 chipset configuration.

        Fix:     Extend the L1 re-entry delay from 8 usec to 16 usec.


Version 4.4.7 (May 02, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Ethernet@Wirespeed does not fallback to 100M link with
                 a broken cable in a system that has the remote PHY 
                 feature enabled (CQ#34668, 5709S).

        Cause:   SerDes has a link resolution problem based on the
                 copper link partner advertisement, thinking that this 
                 is a 1G link. This link mismatch causes the SerDes link
                 to constantly doing auto-negotiation instead of falling
                 back to 100Mbps.

        Fix:     Added workaround to detect this condition and downgrade 
                 the speed advertisement to achieve the correct/final
                 speed.


    2.  Problem: Enabling "PCIE PLL power down" feature too soon.

        Cause:   The 5709 chip is capable to turn off its PLL while 
                 the PCI-E link is in L1. This feature will provide 
                 additional power savings, but due to time constrains 
                 we were not able to fully qualify this feature at this 
                 time. Opting on the safe side, we are disabling this 
                 feature for the time being until we can fully complete 
                 evaluating this feature.
     
        Change:  Disabled the PCIE (L1) PLL power down feature.


    3.  Problem: Virtual MAC does not is not preserved across system 
                 reboot on a blade server design (CQ#35071).

        Cause:   The chip has no WOL and no mgmt FW enabled. As a 
                 result, the boot code brings down the chip to its 
                 minimum power state, possibly erasing the CPU
                 scratchpad content that contains the VMAC information
                 at the point when when the system is powering down.
                 Upon power up from rebooting, the boot code clears
                 out the scratchpad content.

        Fix:     On LOMs, the chip is not brought down the the minimum
                 power state (i.e. playdead) and therefore preserving
                 the VMAC information on the CPU scratchpad area. Also, 
                 a better condition check is added before zeroing out 
                 the scratchpad.


Version 4.4.6 (April 24, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Copper GPHY auto powerdown feature may lead to lock up
                 on some register accesses, although no bug has been
                 reported related to this (5709C).

        Cause:   Those registers rely on presence of the GPHY clock.

        Fix:     Removed the GPHY auto powerdown feature.


    2.  Problem: Remote PHY may intermittently get false link up even
                 though cable is not connected (CQ#34631, 5709S).

        Cause:   Boot code inadvertently link up with the remote PHY
                 module with a forced 1G link.

        Fix:     Removed parallel detection when remote PHY is enabled.


    3.  Problem: With management firmware enabled, some systems may 
                 reboot while running xdiag tests or executing a reset 
                 command from xdiag (CQ#34634).

        Cause:   As boot code loads mgmt firmware, the host is trying to
                 access the NVRAM logic at the same time. The boot code
                 continuously polling the access grant without any delay
                 in between. This causes host access to this logic to 
                 time out on the PCIE side, causing system NMI.

        Fix:     Added delay between polling.


    4.  Problem: There is a unlikely potential that some systems may 
                 assert NMI due to incomplete PCIE transaction when
                 host attempts to access PHY.

        Cause:   The boot code continuously polling the MDIO access
                 completion without any delay in between. This could 
                 cause host access to time out on the PCIE side.

        Fix:     Added delay between polling.


    5.  Problem: A corner case is found with a potential link problem
                 when the initial link configuration in NVRAM is not
                 set to autoneg.

        Cause:   The link preference maintained in boot code may not be
                 initialized if the configuration is set to forced 
                 speed.

        Fix:     Initialize the link preference even for forced speed.


    6.  Problem: NCSI firmware is not able to set link back to gigabit
                 speed through autoneg.

        Cause:   The set link routine did not account for PHY reset 
                 attribute when an autoneg request without specific 
                 advertisement is issued.

        Fix:     Fixed to honor the reset attribute to allow the link
                 to be re-established.


    7.  Problem: DOS driver is mis-reporting link information.

        Cause:   The autoneg enable bit in the SerDes is left at its
                 hardware default. In earlier version (v4.4.0 and 
                 before), the boot code initialized the bit.

        Fix:     Initialize the autoneg enable bit as a part of the 
                 PHY/SerDes initialization routine.


    8.  Problem: Boot code may mis-handle requests from a different
                 port.

        Cause:   The error handling in the link setting routine has a
                 potential of not restoring the port context.

        Fix:     Ensure port context restoration in error handling.


    9.  Problem: Remote PHY may establish link with an incorrect link
                 preference. This could result in getting a gigabit link
                 when 100M is requested (5709S).

        Cause:   The preference detection scheme swings between copper
                 and SerDes preferences when the copper cable is 
                 disconnected. When connected, the swing could land on
                 SerDes preference, and it will be used for the setting.

        Fix:     Improve the detection scheme by checking for possible
                 extended autoneg when the link is up. If no extend
                 autoneg, ensure SerDes preference is applied; 
                 otherwise, ensure copper preference is applied.


    Enhancements:
    -------------
    1.  Request: Improve on power savings from the PCIE block.

        Changes: Enable PCIE PLL auto powerdown on chip hard resets
                 for both functions.

        Impact:  No major functional impact from the boot code 
                 perspective.


Version 4.4.5 (April 18, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Boot code stalls when IPMI is enabled (5709 C/S).

        Cause:   Phase two of the boot code collides with IPMI FW on the
                 scratchpad, and stack is corrupted as a result.

        Fix:     Optimize the code and move the phase two location back
                 to the original place.


    2.  Problem: PHY loopback test on BACS intermittently failed on 
                 remote PHY platform (CQ#34816, 5709S).

        Cause:   Boot code did not account for driver owning the SerDes.
                 Hence, the boot code changes the SerDes setting causing
                 the failure of packet returns.
                 
        Fix:     Added better checking to make sure driver acknowledges
                 SerDes ownership.


    3.  Problem: Management firmware fails to load on some Bx revision
                 chips, and configuration of enabling/disabling NCSI
                 does not work on one mezz design (CQ#34788, 5709 C/S).

        Cause:   There appears to be a problem with Bx chips handling
                 CAM BIST. The boot code halts and stops loading any
                 management firmware.
                 
        Fix:     Modified to perform CAM BIST only on revision C0 and
                 after.


    4.  Problem: Windows driver flow control does not work as expected
                 on a remote PHY platform (CQ#34669, 5709S).

        Cause:   The remote PHY setting is not re-initialized even
                 though the driver requests so. Also, the flow control
                 logic is not propagating pause setting correctly.
                 
        Fix:     Fixed the flow control setting logic and to honor 
                 driver request to re-initialize the SerDes.


    5.  Problem: BACS loopback test failed when the other port is
                 continuously undergoing driver load/unload (CQ#34757,
                 5709 C/S).

        Cause:   Boot code temporarily ignored driver communication on
                 one port when the other one is going through 
                 diagnostic tests. This caused timeout on the 
                 synchronization with the driver while it is loaded.
                 
        Fix:     Fixed to continue monitor driver communication on the
                 other port.


Version 4.4.4 (April 09, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Boot code incorrectly indicates the need of having a
                 low power link. However, no issues are found related to
                 this incorrect behavior.

        Cause:   It did not clear the low power link indication when the
                 the chip is back to full power state. 

        Fix:     Clear the indication when chip is in full power state.


    2.  Problem: S5 WOL does not work on LOMs (CQ#34440, CQ#34433, 
                 CQ#34702).

        Cause:   (1) Boot code fails to re-sets the MCP enable bit to 
                 allow unprepared powerdown interrupt to come in. 
                 Without the interrupt due to S5, the boot code cannot 
                 put the chip back to WOL mode. (2) In some cases, the
                 WOL event is detected, but the interrupt is armed too
                 soon. The bouncing of the PERST# signal triggers the
                 interrupt, causing the boot code to restart. Thinking
                 this being an WOL case again, the boot code indirectly
                 drives SEL_VAUX#. Some systems cannot fully power up
                 when this signal is asserted.

        Fix:     (1) Set the MCP enable bit on every port reset. (2) 
                 Take out the condition that allows immediate interrupt
                 arming when PME# (WOL wakeup) is asserted.


    3.  Problem: The interrupt arming condition does not work well in 
                 Vaux state.

        Cause:   The timer block is inactive during Vaux state, 
                 returning the same value.

        Fix:     Use the MCP tick count in Vaux state to determine the
                 time.


    4.  Problem: Run out of code space based on the current 
                 starting address.

        Cause:   All the fixes and code changes have increased the code
                 size, exceeding the size limit on the scratchpad.

        Fix:     Moved the phase two boot code starting address to allow
                 more code space by 2kB.


Version 4.4.3 (April 03, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Remote PHY blade servers failed to establish link with
                 various switches (CQ#33532, 5709S).

        Cause:   Boot code was switching between remote PHY and serdes
                 modes too fast. This did not give enough time to 
                 establish 100m link. The problem is seen when trying
                 to establish 10/100 link, not 1G. 

        Fix:     Fixed the sampling period check algorithm, and adjusted 
                 the sampling time period.


    2.  Problem: Remote PHY blade servers failed to establish link with
                 10/100 switches after establishing a 1G link with 
                 another partner (5709S).

        Cause:   Boot code initially established 1G link via serdes 
                 mode. Once in the serdes mode, it cannot establish link
                 when connecting to 10/100 switches.

        Fix:     Fixed to force to remote PHY mode when talking to a 
                 remote PHY module.


    3.  Problem: Windows shows remote PHY link when cable is not 
                 connected.

        Cause:   The link change interrupt, generated by hardware, went 
                 to the driver too soon. The boot code did not have a 
                 chance to update the link status in time. Thus, the 
                 driver read a stale link status.

        Fix:     After the link status update, the boot code triggers
                 another interrupt to the driver to ensure the driver
                 gets the correct information. Although the problem 
                 occurs only on remote PHY application, the fix is 
                 changing the underlying driver pulse interrupt 
                 mechanism, even though there should be no functional
                 impact.


Version 4.4.2 (March 31, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: The LED shows a color different from that of 5708
                 (CQ#34126, 5709C).

        Cause:   The link setting parameter to the PHY is invalid; thus,
                 the link is back to 10, just as the hardware default.

        Fix:     Fixed the copper link setting parameter to make sure
                 the code carries out the PHY link initialization.


    2.  Problem: Boot code failed to recognize driver presence after
                 running driver load/unload in xdiag.

        Cause:   The driver pulse related counters are not initialized
                 when handshaking with the driver during loading 
                 sequence.

        Fix:     Initialize these counters.


    Enhancements:
    -------------
    1.  Request: Enable BIST.

        Changes: Zero'ing out most of the memory blocks in the chip and 
                 is useful to check for parity errors.

        Impact:  Added code size in bc1. 


    2.  Request: Apply power saving modes (5709C).

        Changes: Apply early DAC feature for C0 at appropriate places
                 and turn on PHY auto powerdown mode even for gigabit
                 OOB WOL.

        Impact:  Provide power savings in WOL mode.


    3.  Request: Support 5716.

        Changes: Check for the new bond ID and disable licensing 
                 support.

        Impact:  License are not validated; thus, no offload feature is
                 allowed.


Version 4.4.1 (March 04, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Windows WOL does not work (CQ#33921).

        Cause:   Boot code mistreated the WOL state and used NVRAM WOL
                 setting, instead of driver WOL setting, to determine 
                 whether to power down the PHY or not.

        Fix:     Fixed to catch driver WOL setting in Windows going to
                 sleep states.

    Enhancements:
    -------------
    1.  Request: Add remote PHY and inband MDIO support (5709S).

        Changes: Added support into serdes to handle remote PHY link
                 auto-negotiation. Also added the state to maintain
                 copper and serdes link preferences.

        Impact:  Added a significant amount of code. The change could
                 have impact on 5709C as some portions of the set link
                 codes are restructured.


    2.  Request: Support set_link call for mgmt FW to allow enabling
                 link auto-negotiation without having to specify the
                 capability advertisement.

        Changes: Store the prior advertisement setting and apply it 
                 when needed.

        Impact:  Store the prior advertisement setting and assume 
                 full advertisement (unless NVRAM parameter specifies
                 otherwise) as the initial setting.


    3.  Request: Dynamically track the KEEP_VLAN_TAG bit in Rx path in 
                 the shared memory so that mgmt FW can decide how to 
                 process incoming packets. The earlier version only 
                 allows updates on driver load/unload.

        Changes: Define a new driver command to notify the change in
                 the KEEP_VLAN_TAG state.

        Impact:  The original KEEP_VLAN_TAG capability advertised by
                 the boot code is removed, and a new capability is 
                 introduced.


    4.  Request: VMAC needs to take effect immediately rather than
                 relying on a chip reset.

        Changes: Update the EMAC perfect match filter immediately after
                 seeing the command issued by the host.

        Impact:  No reset is needed to take effect, although the extra
                 reset does no harm.


    5.  Request: Need to statically assign the pre-emphasis and idriver
                 values in blade server applications (5709S).

        Changes: Program the Tx driver register in the serdes with a 
                 static value stored in the NVRAM.

        Impact:  None.


Version 4.4.0 (February 12, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Host traffic stops when Windows comes back from S3/S4
                 with IPMI enabled (CQ#32944).

        Cause:   Driver failed to post WAIT0 message, misleading the 
                 boot code to route all packets to mgmt FW.

        Fix:     Although the fix is already done in driver, the missing
                 WAIT0 should not lead routing of all packets to mgmt 
                 FW. Clear the routing when detecting further driver
                 handshake messages.


    2.  Problem: NVRAM inventory check for MBA is not returning the same
                 version format compared to other images.

        Cause:   The version value is shifted.

        Fix:     Corrected it to match the same version format.


    3.  Problem: WOL does not work in 5709S. The SPIO2 is not driven low
                 in that state. A similar issue may be seen in 5709C.

        Cause:   The power mgmt tracking state machine mistreats the WOL
                 case as unprepared powerdown case, thus not driving
                 SPIO2 on both ports.

        Fix:     Corrected the state machine logic to driver SPIO2 in 
                 WOL case.


    Enhancements:
    -------------
    1.  Request: Support ASPM capability.

        Changes: Re-initialize the PCIE L0s and L1 acceptable latency
                 advertisement.

        Impact:  The area of impact is in PCIE ASPM feature.


    2.  Request: Support clearing of virtual MAC address, allowing the
                 chip to use the default from NVRAM.

        Changes: Defined a new command interface for the host software
                 and restoring the MAC address in shared memory to NVRAM 
                 default.

        Impact:  Boot code needs to recognize the special parameter in
                 the driver/BIOS command interface.


    3.  Request: Include iSCSI boot into the NVRAM inventory check 
                 support (v2.7.4 or above is required).

        Changes: Implemented the version number retrieval from the iSCSI
                 boot image.

        Impact:  Code size increase.


    4.  Request: Put the chip into the lowest power consumption state
                 when in Vaux with no WoL and no mgmt FW enabled.

        Changes: Detect the conditions of Vaux, no WoL, and no mgmt FW,
                 and put the chip into MIN_POWER state on both ports.

        Impact:  The chip is no longer functional once in this mode
                 until a power-on or PCIE reset.


Version 4.1.1 (January 15, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Windows hangs while shutting down (CQ#33431). In 
                 another case, a system hangs after running Chariot
                 tests for a few minutes (CQ#33434).

        Cause:   Tx side of the PCIE posted data flow control credit was
                 initialized to one, causing the root complex to wait 
                 indefinitely for enough (MaxPacketSize) credits to 
                 proceed shutdown sequence or handling traffic.

        Fix:     Leave the posted data credit as default.


Version 4.1.0 (January 11, 2008)
================================
 
    Fixes:
    ------
    1.  Problem: Windows BSOD/NMI when running L4 stress test 
                 (CQ#32922).

        Cause:   Tx side of the PCIE flow control had a problem with 
                 freeing multiple credits at a time. 

        Fix:     This requires boot code workaround, advertising only 
                 one outstanding credit. This workaround is necessary 
                 only for Ax and Bx silicons.


Version 4.0.5 (December 18, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: IPMI connection times out as soon as Windows 
                 diagnostics start (CQ#33085).

        Cause:   Boot code failed to handle the Windows diagnostic case
                 where the driver is unloaded without the device being
                 put to D3 state. Thus, the link is not re-auto-neg'd.
                 This has caused IPMI FW to be stuck within itself while 
                 not processing traffic.

        Fix:     Added the case handling to allow proper link re-
                 negotiation.


Version 4.0.4 (December 07, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: Windows VBD hits an assertion on locating the shared
                 memory (CQ#32954).

        Cause:   Boot code did not re-initialize the shared memory 
                 location field because the signature field was intact
                 after the power loss from system shutdown. This misled
                 boot code into skipping the shared memory location (one
                 bit was off).

        Fix:     Always initialize the shared memory header.


Version 4.0.3 (December 06, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: Bnx2 reported invalid information about mgmt FW via
                 ethtool (CQ#32885).

        Cause:   Boot code copied four extra bytes of information from
                 NVRAM to shared memory, corrupting the mgmt FW version
                 pointer.

        Fix:     Eliminated the extra copy.


Version 4.0.2 (December 04, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: PCIE L0s/L1 acceptable exit latency advertisement
                 on the secondary port is incorrect.

        Cause:   Boot code only programmed the appropriate parameters
                 to the first port.

        Fix:     Program the secondary port as well.


    Enhancements:
    -------------
    1.  Request: Initialize shared memory.

        Changes: Detect for shared memory location signature. If not
                 found, zero out the shared memory.

        Impact:  Mgmt FW may lose states, although it is very unlikely.


    2.  Request: Support NVRAM inventory check used by mgmt FW (except
                 iSCSI boot, a new version format is required).

        Changes: Traverse the NVRAM directory for specific FW or PXE
                 images and build a table of version info. This is 
                 refreshed on boot code restart.

        Impact:  Code size increase.


    3.  Request: Replace all chip codename references with chip numbers.

        Changes: Replace all chip codename references with chip numbers.

        Impact:  Functionally none, only documentation changes.


    4.  Request: Revised the link setting routine to adopt a new set of
                 bit definitions to maintain the interface with drivers
                 on the remote PHY feature.

        Changes: The link setting routine is modified.

        Impact:  The link setup in OS absent case is changed, but the
                 link behavior should be the same.


    5.  Request: Advertise power budget numbers for PCIE.

        Changes: Propagate the PCIE power budget numbers from the NVRAM.

        Impact:  Code size increase.


    6.  Request: Allow bnx2 to manipulate VLAN stripping feature in the 
                 Rx filter (see enhancement in v4.0.0).

        Changes: Advertise the allowance so bnx2 can maintain 
                 compatibility with old boot code and mgmt FW.

        Impact:  Code size increase.


Version 4.0.1 (November 19, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: Ethtool cannot report the proper version string for
                 IPMI FW (CQ#32044).

        Cause:   Boot code failed to propagate the string pointer to
                 the driver in the shared memory.

        Fix:     Locate the version string and initialize the shared
                 memory with the string location.


    2.  Problem: Mgmt FW identity is not updated properly in the shared
                 memory.

        Cause:   The mgmt FW loading scheme updated the FW identity on
                 both instances of the shared memory, even though only
                 one port is enabled.

        Fix:     Fixed the identity update based on whether a port is
                 enabled with mgmt FW or not.


    3.  Problem: MCP may be hung during unprepared powerdown. This
                 problem is found in 5708 (CQ#31827). The same problem
                 may occur in 5709.

        Cause:   An access to the PHY is causing the hang. The powerdown 
                 sequence will reset the entire chip, including the PHY, 
                 making the PHY access irrelevant.

        Fix:     Removed the PHY access that is just before the hard
                 reset.


    4.  Problem: IPMI FW cannot pass traffic on 5708 server design
                 (CQ#31473). In particular, the serial over LAN (SOL) 
                 traffic stops. The same problem may occur in 5709.

        Cause:   Boot code detected an invalid write VPD request and 
                 halted.  As a result, IPMI FW cannot drive SMBus to 
                 respond to BMC, causing an invalid MAC address to be 
                 used in the Rx filter on subsequent reset. The invalid
                 request could be coming from the device itself. The
                 hanging on an invalid VPD write is unnecessary and 
                 prevents boot code to operate.

        Fix:     Ignore the invalid write VPD request on power up since
                 the device does not support VPD writes.


    5.  Problem: Chip becomes inaccessible after changing the BAR size
                 in xdiag, followed by a reset command (CQ#32474).

        Cause:   On the reset command, the boot code restarts and
                 applies the new BAR setting, invalidating the BIOS
                 addressing assignment. That requires system reboot
                 to correct the problem.

        Fix:     Apply new BAR size setting and PCIE IDs only on reboot.


    Enhancements:
    -------------
    1.  Request: The PHY and prepared powerdown management needs cleanup.

        Changes: Device a new state machine to keep up with the changes
                 (e.g. going to D3, going to various OS sleep states,
                 etc.). This is also an attempt to resolve other WOL
                 issues filed in earlier versions (CQ#31824, CQ#31968).

        Impact:  A new design, need to retest everything with the PHY
                 link and WOL.


    2.  Request: Need to add BIOS handshake algorithm for some LOM
                 designs (CQ#32459).

        Changes: Added code to detect commands issued from the BIOS, 
                 similar to what is done in 5708.

        Impact:  None, just code size increase.


    3.  Request: Support VMAC clearing, issued from NCSI.

        Changes: Added a new command bit to allow NCSI to undo the VMAC
                 change (restoring the original MAC addresses).

        Impact:  None, just code size increase.


    4.  Request: B step silicons do not address a PCIE compliance
                 problem.

        Changes: Need to apply workaround on all B steps, besides B0.

        Impact:  None, just a logic check change.


    5.  Problem: LSI team reported that the early DAC feature in copper
                 PHY is still not working in B0 silicon (5709C) 
                 (CQ#28226). Then change in v4.0.0 only applies to rev
                 Ax, B0, and B1. Need to apply to B2 as well.

        Cause:   As stated in the problem above.

        Fix:     Disable the feature for all A and B step silicons. The 
                 chip fix is planned for next revision.
 

Version 4.0.0 (October 22, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: In B0 silicon, PCIE link won't train up, thus device 
                 not seen on some systems (CQ#31832).

        Cause:   PCIE LTSSM gets stuck on polling compliance state.

        Fix:     Workaround is applied to enable auto training.


    2.  Problem: LSI team reported that the early DAC feature in copper
                 PHY is still not working in B0 silicon (5709C) 
                 (CQ#28226).

        Cause:   As stated in the problem above.

        Fix:     Disable the feature for all A and B step silicons. The 
                 chip fix is planned for next revision.
 

    3.  Problem: Drivers can potentially have problem getting the serdes
                 link to work when 2.5G is enabled (5709S).

        Cause:   Boot code is handling serdes link fallback while driver
                 is present.

        Fix:     Removed the handling when driver is present.
 

    4.  Problem: Windows WOL does not work on one port when the other 
                 port is not loaded (CQ#31824).

        Cause:   Boot code fails to commit to a prepared powerdown state
                 because the other port was never put to a low power
                 state. As a result, the chip goes back to OOB mode 
                 (driver WOL setting is lost) when main power is lost.

        Fix:     Changed the logic check for driver not loaded in order
                 to commit to prepared powerdown state.
 

    5.  Problem: Boot code has a potential of dispatching mgmt FW while
                 the chip undergoes a diagnostics (e.g. thru Windows
                 BACS). This may be related to CQ#31906.

        Cause:   Boot code is dispatching mgmt FW unconditionally when
                 a driver is about to reset one port. If the other port
                 is going through diagnostic tests, mgmt FW could 
                 potentially mis-behave due the hardware state on the 
                 diagnostic port.

        Fix:     Prevent the mgmt FW dispatching when either port under-
                 goes diagnostic tests. 
 

    Enhancements:
    -------------

    1.  Enable HC block for mgmt FW. This helps in supporting mgmt FW
        stat command in the OS absent (yet main power present) case.

    2.  Track the KEEP_VLAN_TAG bit in Rx path in the shared memory so
        that mgmt FW can decide how to process incoming packets.

    3.  Added FIO access interface through driver-firmware mailbox to 
        enhance debug.


Version 3.7.0 (September 28, 2007)
================================
 
    Fixes:
    ------
    1.  Problem: License validation fails, preventing offload when
                 virtual MAC address is applied on NICs (CQ#31332).

        Cause:   The license validation algorithm was looking up the
                 MAC address from the shared memory. In the case of
                 virtual MAC address applied, the value is different.
                 Hence, the validation fails. 

        Fix:     Look up the MAC address from the NVRAM instead.


    2.  Problem: Xdiag fails on LSO test on secondary port when that 
                 port has UMP enabled (CQ#31322).

        Cause:   During the driver loading sequence, the boot code was
                 dispatching UMP FW using the secondary port as the
                 context (while it always expects the primary port 
                 context). This misled UMP FW into putting the port into
                 a strange state. As a result, the boot code enabled
                 the packet forwarding, preventing all traffic from 
                 going to the host.

        Fix:     Invoke UMP FW always with the primary port context.


    3.  Problem: BACS Control Registers test intermittently fails on 
                 one 5709 port while the other port has heavy traffic 
                 (CQ#31502).

        Cause:   The boot code is still actively running and possibly 
                 accessing some of the registers.

        Fix:     Once in diagnostic mode, the port is not touched by the
                 boot code except for checking on driver unload event.


    4.  Problem: Shared memory for the secondary port does not get
                 information about which mgmt FW is currently running.

        Cause:   Boot code only updates the information on the primary
                 port.

        Fix:     Update both instances of the shared memory.


    5.  Problem: Driver may not receive traffic in some scenarios when
                 mgmt FW is enabled.

        Cause:   The boot code inadvertently enables automatic packet
                 forwarding, routing all traffic to mgmt FW.

        Fix:     Check for driver absence before committing to the 
                 automatic packet forwarding.


    6.  Problem: Windows diagnostic test may fail intermittently.

        Cause:   Boot code is monitoring activities on the port that
                 is in diagnostic mode. As a result, some registers
                 may get modified by boot code, causing failure in the
                 diagnostic tests.

        Fix:     Skip processing anything on that port except for 
                 monitoring for test completion.


    7.  Problem: Port swapping and function hidden features may 
                 inadvertently kick in during xdiag reset command.

        Cause:   Boot code updates those two features (only on enable)
                 whenever boot code is restarted (e.g. xdiag reset
                 command).

        Fix:     Gate all PCIE related features to refresh only on PCIE
                 or power-on reset.


    Enhancements:
    -------------

    1.  Enable full clock rate in Vaux state for LOM designs.
    2.  Port swapping and function hide can now be disabled thru warm
        reboot after NVRAM configuration.


Version 0.4.4 (September 07, 2007)
=================================

    Fixes:
    ------
    1.  Problem: IPMI traffic stops after PXE unloads (CQ#31157).

        Cause:   After the shutdown sequence as PXE unloads, it also
                 issues a reset to the chip. That disables the necessary
                 blocks to allow IPMI traffic to go through.
                 
        Fix:     Enhance the port reset handling to re-enable the 
                 hardware blocks if IPMI is enabled.
 

    Enhancements:
    -------------

    1.  Added OOB virtual MAC support, require mgmt FW to invoke this.
    2.  Support port specific link manipulation for mgmt FW.


Version 0.4.3 (August 16, 2007)
=================================

    Fixes:
    ------
    1.  Problem: OOB WOL does not work (CQ#30966).

        Cause:   With management firmware disabled, the boot code 
                 terminates itself after setting the WOL, but the link
                 may not be completely stable at that time. As a result,
                 incorrect EMAC setting may be used. This prevents WOL
                 packets from getting to the WOL detection circuit.
                 
        Fix:     Allow boot code to continue to operate. This will give
                 the chip to adopt to different link speed and update
                 the EMAC setting accordingly.
 

Version 0.4.2 (August 07, 2007)
=================================

    Fixes:
    ------
    1.  Problem: Driver does not get link when it comes up and only
                 does on subsequent reload (CQ#30244, CQ#30684).

        Cause:   Boot code invertently disables link change attention,
                 preventing any link change events from going to driver.

        Fix:     Preserve the link change attention bit.
 

    2.  Problem: Driver may observe memory parity errors.

        Cause:   Boot code invertently enabled memory parity check
                 without running memory BIST.

        Fix:     Temporarily disable parity check until memory BIST is
                 completely checked out.
 

    3.  Problem: LSI team reported that the early DAC feature in copper
                 PHY is still not working in A1 silicon (5709C).

        Cause:   As stated in the problem above.

        Fix:     Disable the feature for all A step silicons. The chip
                 fix is planned for next revision.
 

    4.  Problem: IPMI connection is lost when Windows goes to S4 or S5
                 (CQ#30253, CQ#30259).
                 
        Cause:   Link setup and mgmt packet forwarding are not handled 
                 properly when driver is unloaded with WOL enabled. 
                 Also, the event notification is not enabled in this 
                 case.
                 
        Fix:     Add link setup, enable packet forwarding, and enable
                 notification of events to allow IPMI FW to handle 
                 traffic.


    Enhancements:
    -------------

    1.  Added virtual MAC support.
    2.  Allow enabling/disabling of beacon.
    3.  Implemented a new mgmt FW loading scheme based on the NVRAM
        configurations.


Version 0.4.1 (June 08, 2007)
=================================
 
    Fixes:
    ------
    1.  Problem: IPMI FW fails to retain filter after power state change
                 (CQ#29669).

        Cause:   In one case, the firmware interrupt setup sequence was 
                 incorrect (enabling it before completing the setup),
                 and an event triggers the interrupt just right after 
                 it is enabled. This caused processor to execute an
                 undesirable location. In another case where the system
                 is powering down to Vaux, the boot code detected the
                 "unprepared powerdown" condition and issued a power-on
                 reset. On the next boot code restart from this reset,
                 the IPMI invalidated its configuration settings,
                 including BMC MAC address. Thus, filters are not
                 programmed.

        Fix:     There are two fixes. One is to correct the interrupt
                 setup sequence to enable it only after the setup is 
                 complete. The second one is to treat the reset from
                 the "unprepared powerdown" as a different one from the
                 true power-on reset.


    2.  Problem: IPMI stops passing traffic after driver load/unload
                 (CQ#29499).

        Cause:   On driver load/unload, some of the hardware blocks are
                 reset back to disabled state. Thus, the management
                 traffic path stops. Also, they are back to reset states
                 that require management to re-apply its configuration 
                 settings (e.g. rule filters).

        Fix:     The boot code re-enables those hardware blocks and 
                 notifies management firmware that a reset occurred so
                 that it can re-apply any configurations.


    Enhancements:
    -------------

    1.  Dispatch management firmwware once more just prior to driver
        issuing a port reset to the chip, allowing the firmware to do
        any cleanup if necessary.

    2.  Initialized the ASPM L0s and L1 acceptable latency settings as
        requested by LSI team.

    3.  Provide an indication on which management firmware is currently
        loaded and running.


Version 0.4.0 (May 23, 2007)
=================================
 
    Fixes:
    ------
    1.  Problem: Management firmware stops running after driver is
                 loaded.

        Cause:   Certain hardware blocks are reset as a result of the
                 driver being loaded, but management firmware has no
                 indication of such an event.

        Fix:     Boot code uses one register bit to detect for the core
                 reset. When that occurs, it will indicate the event to
                 management firmware. 


    2.  Problem: Memory parity is disabled after driver load.

        Cause:   The parity enable is cleared on core reset. It needs
                 to be re-enabled.

        Fix:     Re-enable parity checks on every core reset.


    3.  Problem: WOL could be consuming too much power.

        Cause:   Early DAC needed for running 10Mbps is disabled while
                 the chip goes to sleep state.

        Fix:     Re-enable early DAC on the PHY when going to WOL state
                 without gigabit link.


    4.  Problem: Management firmware could be running at a low speed on
                 LOM.

        Cause:   The management clock is running half the speed to keep
                 power consumption within PCIE limit.

        Fix:     Properly bump up the clock rate for LOMs that have 
                 enough Vaux power.


    5.  Problem: Management firmware does not pass traffic on the
                 second port (CQ#28939).

        Cause:   Boot code fails to report correct link status on that 
                 port.

        Fix:     Add the link status checking on that port.


    6.  Problem: The PHY may not work properly after Linux driver is
                 reloaded the second time.

        Cause:   The first unload may have brought the PHY into a low
                 power state, but the boot code does not bring the PHY
                 back to normal state on the second load.

        Fix:     Add a routine to restore the PHY into normal operation.


    7.  Problem: WOL may not work on unprepared powerdown for LOMs.

        Cause:   The unprepared powerdown feature is not activated.

        Fix:     Activate it.


    8.  Problem: WOL does not work on A1 (CQ#29574).

        Cause:   The GPIOs 0 and 1 were swapped on A0. It was decided
                 the two pins will remain swapped for all revisions.
                 Boot code was initially gating the swap only on A0. 
                 This effectively reverses the power switching scheme.
                 As a result, Vaux is cut off when WOL is enabled on A1.

        Fix:     Eliminate the A0 qualification.


    9.  Problem: ISCSI boot information is lost when Linux driver is
                 loaded again from sleep state.

        Cause:   A chip reset occurs when it goes from D3Hot->D0. That 
                 reset is mis-treated as a warm reboot, and iSCSI boot
                 information is wiped out as a result.

        Fix:     Improve on the warm reboot qualification, gating on 
                 PCIE reset.


   10.  Problem: Boot code intermittently stops.

        Cause:   The delay routine is catching an invalid clock setting
                 because boot code is in the middle of cranking up the
                 core clock.

        Fix:     The delay routine dynamically chooses between clock
                 source based on the power state. It also allows 
                 source preference from the caller. This allows the
                 clock cranking routine to use a stable clock.


   11.  Problem: Some versions of Linux drivers may not pass traffic on 
                 A1.

        Cause:   The DMA enable bit in A1 is introduced, but drivers 
                 did not account for that.

        Fix:     On driver load, boot code will enable DMA.


    Enhancements:
    -------------
    1.  Added serdes support.
    2.  Gate PCIE Gen2 capability on NVRAM configuration.
    3.  Support function hide (only on second port).
    4.  Support WOL beacon based on NVRAM configuration.
    5.  Extended driver heartbeat timeout to 1.5 seconds for Linux
        drivers.


Version 0.3.0 (January 25, 2007)
=================================
 
    Fixes:
    ------
    1.  Problem: Device does not show up on some systems intermittently
                 (CQ#28181).

        Cause:   Certain PCIE serdes registers are not initialized by
                 the hardware.

        Fix:     Added initialization.


    2.  Problem: False PCIE errors detected.

        Cause:   The error status registers of the PCIE digital block
                 was not initialized by the hardware.

        Fix:     Added codes to initialize them on POR.


    3.  Problem: Traffic at 10BT (if applicable) may not be reliable
                 (CQ#28189).

        Cause:   The 10BT early DAC wakeup was inadvertently enabled 
                 by the strap on the hardware.

        Fix:     Added code to disable it.


    4.  Problem: Device fails the device serial number capability test
                 (CQ#28240).

        Cause:   The device serial number registers were not initialized.

        Fix:     Initialize them.


    Enhancements:
    -------------
    1.  Request: Support OOB and driver-initiated WOL (CQ#28209).

        Changes: Added codes to support them. 

        Impact:  None.


    2.  Request: Need a more robust method to apply PCIE serdes work-
                 around.

        Changes: Use a new scheme to always write to those PCIE serdes
                 registers as long as main power is available.

        Impact:  It simplifies the checking logic on applying the work-
                 around.


    3.  Request: Need to have a hardware pin to turn on/off the PCIE
                 polling compliance feature (for Gen2 experimentation).

        Changes: Add logic check on SPIO 4.

        Impact:  The check will have to be either moved to some other
                 pin or removed completely since SPIO 4 is already 
                 reserved for other purpose.


Version 0.2.5 (January 10, 2007)
=================================
 
    Fixes:
    ------
    1.  Problem: Xdiag reports copper chip as serdes.

        Cause:   Boot code was reading an uninitialized shared memory
                 field to determine the media type.

        Fix:     Read the NVRAM for configuration value before using
                 that shared memory field.


    2.  Problem: 5709 fails to get PCIE link on some systems.

        Cause:   There could be multiple PCIE resets when such a system
                 comes up. The boot code can apply workaround on the 
                 first reset, but the subsequence ones wipe out the
                 workaround without allowing the boot code to restart.

        Fix:     Allow unprepared powerdown feature to kick in without
                 waiting for the 3-second debounce. However, this is not 
                 a guarantee workaround; certain reset arrangement could
                 still break this recovery scheme. 


Version 0.2.4 (January 02, 2007)
=================================
 
    Fixes:
    ------
    1.  Problem: Ethernet link does not come up when powering up the 
                 system to DOS.

        Cause:   The removal of dual media override also eliminated the
                 PHY address initialization. As a result, the PHY does
                 not get reset and programmed properly.

        Fix:     Re-enable the dual media override along with a fix in 
                 that area.


    Enhancements:
    -------------
    1.  Request: 5709 is capable of running at a faster speed.

        Changes: Changed the PLL clock setting to allow CPU faster.

        Impact:  None.


Version 0.2.3 (December 16, 2006)
=================================
 
    Intermediate release - Temporarily removed (1) dual media override 
                           (no port swap) and (2) PHY powerdown on 
                           detecting unprepared powerdown.
                         - Enable unprepared powerdown feature on NIC.


Version 0.2.2 (December 15, 2006)
=================================
 
    Intermediate release - Capture VPD address correctly.


Version 0.2.1 (December 15, 2006)
=================================
 
    Intermediate release - Skip CAM BIST.


Version 0.2.0 (December 15, 2006)
=================================
 
    Intermediate release - Provide debug trace functionality to mgmt
                           firmware.
                         - Added PCIE serdes workaround.


Version 0.1.0 (December 07, 2006)
=================================
 
    Intermediate release - Support dual port, new shared memory
                           definitions, trace buffer debug capability.


Version 0.0.1 (September 09, 2006)
==================================
 
    Initial release - Support only single port 5709 builds.



